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| CXA3627ER All Band Tuner IC with On-chip PLL Description The CXA3627ER is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner by adopting a small package. Features * Low power consumption (5V, 63mA typ.) * Low noise figure, low distortion characteristics * High gain/low gain selectable * Supports IF double-tuned/adjacent channel trap * Balanced oscillator circuits with excellent oscillation stability * On-chip PLL supports I2C bus * On-chip high voltage drive transistor for charge pump * Frequency step selectable from 31.25, 50 or 62.5kHz (when using a 4MHz crystal) * Low-phase noise synthesizer * On-chip 4-output band switch (output voltage: 5V, current capacity: 13mA) * 32-pin VQFN small package * UHF band switch output switchable Applications * TV tuners * VCR tuners * CATV tuners Structure Bipolar silicon monolithic IC 32 pin VQFN (Plastic) Absolute Maximum Ratings * Supply voltage VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Conditions Supply voltage -0.3 to +5.5 -25 to +75 -55 to +150 610 V C C mW VCC 4.75 to 5.30 V Note: This IC has pins whose electrostatic discharge strength is weak as the operating frequency is high and the high-frequency process is used for this IC. Take care of handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E02846B45 CXA3627ER Block Diagram and Pin Configuration IFOUT ADSW SDA SCL BS2 BS1 32 31 30 29 28 27 26 25 IFIN1 1 IF AMP IFIN2 2 I2C Bus Interface VCC 3 Shift Register Divider 1/128, 160, 256 REF OSC BS3 NC 24 REFOSC Phase Detector Band SW Driver Charge Pump 23 CPO 22 VT MIXOUT1 4 MIXOUT2 5 VHF MIX Programmable Divider 14/15 bit Prescaler 1/2 21 GND2 GND1 6 20 UOSCB2 19 UOSCE2 VHFOSC VHFIN 7 BYP 8 UHFOSC UHF MIX 18 UOSCE1 17 UOSCB1 9 10 11 12 13 14 15 16 BS4 UHFIN1 UHFIN2 NC VOSCB1 VOSCC1 VOSCC2 -2- VOSCB2 CXA3627ER Pin Description Pin No. Symbol Pin voltage [V] 3 Equivalent circuit Description 1 IFIN1 1 1.6k 2 2.0 IF inputs. These pins must be connected to the mixer outputs via coupling capacitance. 2 IFIN2 3 VCC -- 4 -- 5 Power supply. 4 MIXOUT1 -- Mixer outputs. These pins output the signal in open collector format, and they must be connected to the power supply via a load. 5 MIXOUT2 6 GND1 -- 2.4 during VHF reception 0.0 during UHF reception 3 -- Analog circuit GND. VHF input. The input format is unbalanced input. 7 VHFIN 10k 15p 7 3k 3k 100 8 BYP 3.8 (when open) 8 VHF input GND and selection of band switching. GND: BS4 UHF Open: BS3 UHF -3- CXA3627ER Pin No. Symbol Pin voltage [V] 3 Equivalent circuit Description 9 BS4 9 25 25 BS3 High: 4.9 Low: 0.0 3 100k Band switch outputs. This pin corresponding to the selected band goes High. 31 BS1 31 32 32 BS2 3 10 UHFIN1 0.0 during VHF reception 2.3 during UHF reception 10 11 3k 3k 11 UHFIN2 UHF inputs. Input a balanced signal to Pins 14 and 15, or ground either of Pin 14 or 15 with a capacitor and input the signal to the other pin. 12 13 NC VOSCB1 -- 2.3 during VHF reception 2.5 during UHF reception 4.0 during VHF reception VCC during UHF reception 4.0 during VHF reception VCC during UHF reception 2.3 during VHF reception 2.5 during UHF reception 3 20 5k 5k -- 16 15 14 20 13 14 VOSCC1 External resonance circuit connection for VHF oscillator. 15 VOSCC2 16 VOSCB2 -4- CXA3627ER Pin No. 17 Symbol Pin voltage [V] 2.4 during VHF reception 2.2 during UHF reception 2.0 during VHF reception 1.5 during UHF reception 2.0 during VHF reception 1.5 during UHF reception 2.4 during VHF reception 2.2 during UHF reception 20 19 18 17 Equivalent circuit Description UOSCB1 3 18 UOSCE1 19 UOSCE2 3k 3k External resonance circuit connection for UHF oscillator. 20 UOSCB2 24 GND2 -- 3 -- PLL circuit GND. Varicap drive voltage output. This pin outputs the signal in open collector format, and it must be connected to the tuning power supply via a load. 22 VT -- 23 22 70 23 CPO 2.0 Charge pump output. Connects the loop filter. 3 30k 100 25p 24 REFOSC 4.4 24 38p Crystal connection for reference oscillator. 3 150k 26 ADSW 1.25 (when open) 26 50k 5p Address selection. Controls address bits 1 and 2. -5- CXA3627ER Pin No. Symbol Pin voltage [V] 3 Equivalent circuit Description 27 IFOUT 2.8 27 IF output. 28 NC -- 3 -- 29 SCL -- 29 40k Clock input. 3 30 SDA -- 30 40k Data input. 5p -6- CXA3627ER Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.) (Vcc = 5V, IFVCC = 5V, Ta = 25C) Circuit Current Item Symbol Iccv Circuit current Iccu Measurement conditions VCC current Band switch output open during VHF operation VCC current Band switch output open during UHF operation Min. 41 40 Typ. 64 63 Max. 88 87 Unit mA mA OSC/MIX/IF Amplifier Block Item Symbol CG1 CG2 CG3 Conversion gain1 CG4 CG5 CG6 CG7 CG8 NF1 NF2 NF3 Noise figure1, 2 NF4 NF5 NF6 NF7 NF8 CM1 CM2 CM3 CM4 CM5 CM6 CM7 CM8 Maximum output power Measurement conditions VHF operation fRF = 55MHz High gain mode VHF operation fRF = 360MHz High gain mode UHF operation fRF = 360MHz High gain mode UHF operation fRF = 800MHz High gain mode VHF operation fRF = 55MHz Low gain mode VHF operation fRF = 360MHz Low gain mode UHF operation fRF = 360MHz Low gain mode UHF operation fRF = 800MHz Low gain mode VHF operation fRF = 55MHz High gain mode VHF operation fRF = 360MHz High gain mode UHF operation fRF = 360MHz High gain mode UHF operation fRF = 800MHz High gain mode VHF operation fRF = 55MHz Low gain mode VHF operation fRF = 360MHz Low gain mode UHF operation fRF = 360MHz Low gain mode UHF operation fRF = 800MHz Low gain mode VHF operation fD = 55MHz fUD = 12MHz (30% AM) High gain mode VHF operation fD = 360MHz fUD = 12MHz (30% AM) High gain mode UHF operation fD = 360MHz fUD = 12MHz (30% AM) High gain mode UHF operation fD = 800MHz fUD = 12MHz (30% AM) High gain mode VHF operation fD = 55MHz fUD = 12MHz (30% AM) Low gain mode VHF operation fD = 360MHz fUD = 12MHz (30% AM) Low gain mode UHF operation fD = 360MHz fUD = 12MHz (30% AM) Low gain mode UHF operation fD = 800MHz fUD = 12MHz (30% AM) Low gain mode -7- 99 99 97 94 100 100 98 94 8 Min. 19.0 19.5 23.0 23.0 17.0 17.5 21.0 21.0 Typ. 22.0 22.5 26.0 26.0 20.0 20.5 24.0 24.0 12 12 10 11 13 13 11 12 103 103 101 98 104 104 102 98 11 Max. 25.0 25.5 29.0 29.0 23.0 23.5 27.0 27.0 15 15 13 14 16 16 14 15 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm 1% cross modulation 11, 3 Pomax 50 load, saturation output CXA3627ER Item Symbol fsw1 Measurement conditions VHF operation fOSC = 100MHz f from 3s to 3min after switch ON VHF operation fOSC = 405MHz f from 3s to 3min after switch ON UHF operation fOSC = 405MHz f from 3s to 3min after switch ON UHF operation fOSC = 845MHz f from 3s to 3min after switch ON VHF operation fOSC = 100MHz f when VCC 5V changes 5% VHF operation fOSC = 405MHz f when VCC 5V changes 5% UHF operation fOSC = 405MHz f when VCC 5V changes 5% UHF operation fOSC = 845MHz f when VCC 5V changes 5% VHF operation 10kHz offset CP = 1 Phase comparison frequency = 31.25kHz UHF operation 10kHz offset CP = 1 Phase comparison frequency = 31.25kHz Min. Typ. Max. 200 650 350 400 100 350 100 100 Unit kHz kHz kHz kHz kHz kHz kHz kHz dBc/Hz dBc/Hz Switch ON drift (PLL not operating) 4 fsw2 fsw3 fsw4 fst1 Supply voltage drift fst2 (PLL not operating) 4 fst3 fst4 C/N1 Oscillator phase noise C/N2 80 80 1 Value measured with untuned input. 2 NF meter direct-reading value (DSB measurement). 3 Value with a desired reception signal input level of -30dBm, an interference signal of 100kHz/30% AM, and an interference signal level where S/I = 46dB measured with a spectrum analyzer. 4 Value when the PLL is not operating. -8- CXA3627ER PLL Block Item Symbol LUT1 Lock-up time LUT2 Reference leak CL and DA inputs "H" level input voltage "L" level input voltage "H" level input current "L" level input current AD input "H" level input voltage "L" level input voltage "H" level input current "L" level input current SDA output "H" output leak current "L" output voltage CPO (charge pump) Output current 1 Leak current 1 Output current 2 Leak current 2 VT (VC voltage output) Maximum output voltage Minimum output voltage REFOSC Oscillation frequency range Input capacitance Negative resistance Band SW Output current Saturation voltage Leak current IBS VSAT LeakBS When ON When ON Source current = 13mA When OFF IFVCC = 5.5V 250 0.5 -13 330 3 mA mV A FXTOSC CXTOSC RNEG Crystal source impedance fREF = 4MHz 3 22 -1 24 -3 12 26 MHz pF k VTH VTL Sink current = 1mA 0.15 34 0.8 V V ICPO1 ICPO2 When CP = 0 is selected When CP = 1 is selected 30 120 50 200 80 30 320 100 A nA A nA LeakCP1 When CP = 0 is selected LeakCP2 When CP = 1 is selected ISDALK VSDAL VIN = 5.5V Sink = -3mA GND 5 0.4 A V VIH VIL IIH IIL VIH = Vcc VIL = GND 3 GND 100 -35 Vcc 1 200 -100 V V A A VIH VIL IIH IIL VIH = Vcc VIL = GND 3 GND 0 -0.2 Vcc 1.5 -0.1 -4 V V A A REFL Measurement conditions VHF operation CP = 1 fOSC 100MHz fOSC 405MHz UHF operation CP = 1 fOSC 405MHz fOSC 845MHz Phase comparison frequency = 31.25kHz CP = 1 50 Min. Typ. Max. 50 50 Unit ms ms dBc -9- CXA3627ER Item Bus timing (I2C bus) SCL clock frequency Start waiting time Start hold time Low hold time High hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time Symbol fSCL Measurement conditions Min. 0 1300 600 1300 600 600 0 600 Typ. Max. 400 Unit kHz ns ns ns ns ns tW;STA tH;STA tLOW tHIGH tS;STA tH;DAT tS;DAT tR tF tS;STO 900 300 300 ns ns ns ns ns 600 - 10 - CXA3627ER Electrical Characteristics Measurement Circuit +30V 22k 4700p 240 0.056 10k 220n 10k 2.5 2.5T 0.5p 10k 1T363 1T363 10k 1n 0.5p BS1 3.0 5.5T 2.5 2.5T 100p 100p 24 23 22 21 20 7p 19 2p 18 7p 2.2n 17 4.7k 1n 8p 1T363 1T362 15p 27 4.7k 4.7k BS2 1k 1n 0.5p XTAL 4MHz 56p 7p 56p REFOSC CPO VT GND2 UOSCB2 UOSCE2 UOSCE1 360 25 BS3 ADSW 1n IF OUT 26 ADSW 27 IFOUT 28 NC 51 VOSC 16 B2 VOSCC2 15 VOSCC1 14 VOSCB1 13 NC 12 SCL 51 SDA 360 29 SCL 30 SDA 31 BS1 360 BS1 BS2 UOSC B1 UHF IN UHFIN2 11 1n UHFIN1 10 1n MIXOUT1 MIXOUT2 IFIN1 IFIN2 BYP VCC 32 BS2 VHFIN GND1 BS4 9 360 1 2 1n 3 4 5 6 7 8 1n 1n 150p 4.5T 4.5T 150p 56p 56p 1n 4.7 +5V 100 1n VHF IN - 11 - CXA3627ER Application Circuit +30V 22k 4700p 240 0.056 10k 220n 10k 2.5 2.5T 0.5p 10k 1T369 1n BS1 3.0 5.5T 2.5 2.5T 100p 100p 24 23 22 21 20 22p 19 8p 18 8p 2.2n 17 4.7k 1n 8p 1T363 1T362 15p 27 4.7k 4.7k BS2 1k 1n 0.5p 12p XTAL 4MHz 100p 100p CPO UOSCB2 UOSCE2 FMT 3k ADSW IF OUT 1.2H 10p 1n 25 BS3 REFOSC UOSCE1 26 ADSW 27 IFOUT 28 NC 200 VOSC 16 B2 VOSCC2 15 VOSCC1 14 VOSCB1 13 NC 12 SCL SDA BVL 47p 47p 29 SCL 200 30 SDA 31 BS1 UOSC B1 VT GND2 UHF IN UHFIN2 11 1n UHFIN1 10 1n MIXOUT1 MIXOUT2 IFIN1 BS2 1 2 1n 3 4 5 6 7 3.8 14.5T 33p 150p 3.2 7.5T 1n 2k 4.5T 4.5T 1n 1n 56p 56p 1n 4.7 +5V 100 1n VHF IN Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 12 - BYP VCC BS1 IFIN2 BVH 32 BS2 VHFIN GND1 BS4 9 BU 8 CXA3627ER Description of Functions The CXA3627ER is the terrestrial TV broadcasting tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF and UHF band signals. In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillation frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal. 2. Local oscillation circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. 4. PLL circuit This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports the I2C bus format. The frequency steps of 31.25, 50 or 62.5kHz can be selected by the I2C bus data-based reference divider frequency division setting value. 5. Band switch circuit The CXA3627ER has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data. The emitters for these PNP transistors are connected to the power supply pin (VCC), and are ON and output 5V when the bus data is "1 (H)". Two types of relations of the bus data and the IC internal OSC/MIX circuits operation are available as shown below. These relations can be selected by grounding or leaving open Pin 8 (BYP). BYP: Grounding Band SW data BS1 BYP: Open Band SW data BS1 : Don't care BS2 BS3 0 1 O: Operating BS4 MIX circuit VHF O X UHF X O - 13 - OSC circuit VHF O X UHF X O BS2 BS3 BS4 0 1 MIX circuit VHF O X UHF X O OSC circuit VHF O X UHF X O X: Not operating CXA3627ER Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.) VHF oscillator circuit * This is the differential amplifier-type oscillator circuit. Pins 13 and 16 are base and Pins 14 and 15 are collector. Pins 13, 15 and Pins 16, 14 have the in-phase input/output relation respectively. This circuit is oscillated with the positive feedback applied by connecting the output to the input via the coupling capacitor and the feedback capacitor. Oscillation frequency is varied by connecting an LC parallel resonance circuit including a varicap and controlling the voltage applied to the varicap. VHF mixer circuit * The mixer circuit employs a double balanced mixer with little local oscillation signal leakage. The input format is base input type, with Pin 8 grounded either directly or via a capacitor and the RF signal input to Pin 7. (Pin 8 can also be used to select VHF/UHF switching mode with the BS3/BS4 data.) * The RF signal is fed from the oscillator, converted to IF frequency and output from Pins 4 and 5. Pins 4 and 5 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 4 and 5. UHF oscillator circuit * The oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap. * Resonance capacitance is connected between Pins 17 and 18, Pins 18 and 19, and Pins 19 and 20, and an LC resonance circuit including a varicap is connected between Pins 17 and 20. UHF mixer circuit * This circuit employs a double balanced mixer like the VHF mixer circuit. The input format is base input type, with Pins 10 and 11 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 10 and 11 or unbalanced input consisting of grounding Pin 10 via a capacitor and input to Pin 11. * Pins 4 and 5 are the mixer outputs. Pins 4 and 5 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 4 and 5. IF amplifier circuit * Pins 1 and 2 are the IF amplifier inputs, and the input impedance is approximately 1.6k. * The signals frequency converted by the mixer are output from Pins 4 and 5, and Pins 4 and 5 are connected to Pins 1 and 2 via capacitors. (An adjacent channel trap circuit can be formed by connecting LC parallel circuits in place of capacitors.) * The signal amplified by the IF amplifier is output from Pin 27. The output impedance is approximately 10. - 14 - CXA3627ER Description of PLL Block This IC is controlled by the I2C bus. The PLL of this IC performs high-speed phase comparison, providing low reference leak and quick lock-up time characteristics. During power on, the power-on reset circuit operates to initialize the frequency data to all "0" and the band data to all "OFF". Power-on reset is performed when VCC 3.2V at room temperature (Ta = 25C). 1) Address setting Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one system. The responding address can be set according to the ADSW pin voltage. Address 1 1 0 0 0 MA1 MA0 R/W Hardware bits ADSW pin voltage 0 to 0.1Vcc OPEN or 0.2Vcc to 0.3Vcc 0.4Vcc to 0.6Vcc 0.9Vcc to Vcc MA1 0 0 1 1 MA0 0 1 0 1 2) Frequency data setting The VCO lock frequency is obtained according to the following formula. fosc = 2 x fref x (32M + S) fosc: local oscillator frequency fref: phase comparison frequency M: main divider frequency division ratio S: swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. S < M 1023 0 S 31 - 15 - CXA3627ER 3) Control format When performing control for this IC, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data. These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5. When the correct address is received and acknowledged, the data is recognized as frequency data if the first bit of the next byte is "0", and as control data and band switch data if this bit is "1". Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once the control and band switch data have been programmed, 3-byte commands consisting of the address and frequency data are possible. Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions and the new address. The control format is as shown in the table below. Slave Receiver MSB Mode Address byte Divider byte1 Divider byte2 Control byte Band SW byte bit 7 1 0 M2 1 X bit 6 1 M9 M1 CP X bit 5 0 M8 M0 GC X bit 4 0 M7 S4 CD X bit 3 0 M6 S3 X BS4 bit 2 MA1 M5 S2 R1 BS3 bit 1 MA0 M4 S1 R0 BS2 LSB bit 0 0 M3 S0 OS BS1 A A A A A X: Don't care A: MA0, MA1: M0 to: S0 to: CD: OS: CP: GC: BS1 to BS4: R0, R1: Acknowledge bit address setting main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump OFF (when "1") varicap output OFF (when "1") charge pump current switching (200A when "1", 50A when "0") gain switching (IC gain reduced by 2dB when "1") band switch control (output PNP transistor ON when "1") reference divider frequency division ratio setting (See the Reference Divider Frequency Division Ratio Table.) Reference Divider Frequency Division Ratio Table R1 0 1 X R0 1 1 0 Reference Divider 256 128 160 X: Don't care - 16 - CXA3627ER I2C Bus Timing Chart tW;STA SDA tS;STA tR tF tS;STO SCL tH;STA START tS;STA tW;STA tH;STA tLOW tHIGH tLOW tHIGH tS;DAT tH;DAT STOP CLOCK tS;DAT tH;DAT tS;STO tR tF DATA CHANGE = Data setup time = Data hold time = Stop setup time = Rise time = Fall time = Start setup time = Start waiting time = Start hold time = Low clock pulse width = High clock pulse width - 17 - CXA3627ER Example of Representative Characteristics Circuit current vs. Supply voltage 70 68 66 Icc - Circuit current [mA] Band SW output voltage vs. Output current (BS1, BS2, BS3, BS4) 5.4 Vcc = 5V VHF UHF Output voltage [V] 5.3 5.2 64 62 60 58 56 54 52 50 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.1 5.0 4.9 4.8 4.7 4.6 0 3 6 9 12 15 18 Vcc - Supply voptage [V] Output current [mA] 40 Conversion gain vs. Reception frequency (Untuned input) fIF = 45MHz High gain mode 20 Noise figure vs. Reception frequency (Untuned input, in DSB) fIF = 45MHz High gain mode CG - Conversion gain [dB] UHF VHF (High) NF - Noise figure [dB] 30 15 VHF (High) VHF (Low) UHF 20 VHF (Low) 10 10 5 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] Next adjacent cross modulation vs. Reception frequency (Untuned input) 120 110 100 CM - Cross modulation [dB] VHF (High) VHF (Low) UHF Oscillation frequency power supply fluctuation (PLL off) 400 300 VHF (High) Vcc + 5% Vcc - 5% (Vcc = 5V) 90 +B drift [kHz] 200 VHF (Low) 80 70 60 50 40 30 20 10 0 0 fIF = 45MHz High gain mode 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] fUD = fD + 12MHz fUD = fD - 12MHz (100kHz, 30% AM) 100 UHF 0 -100 -200 -300 -400 0 100 200 300 400 500 600 700 800 900 Oscillation frequency [MHz] - 18 - CXA3627ER Oscillator phase noise vs. Reception frequency (untuned input) 130 120 C/N - Oscillator phase noise [dBc/Hz] fIF = 45MHz High gain mode VHF (Low) VHF (High) UHF 110 100 90 VHF (High) VHF (Low) UHF 80 70 VHF (Low) VHF (High) UHF 60 50 40 0 100 200 300 400 500 1kHz offset 10kHz offset 100kHz offset 600 700 800 900 Reception frequency [MHz] I/O characteristics (untuned input) 20 20 PCS beat characteristics (untuned input) High gain mode 10 10 0 0 -10 IF output level [dBm] fIF -10 -20 -30 -40 fBeat -50 -20 -30 -40 fRF = 45MHz High gain mode fRF = 145MHz (VHF) fRF = 495MHz (UHF) -60 -70 -80 -40 fLocal = 495MHz fP = 449.25MHz fc = 452.83MHz (fP -12dB) fs = 453.75MHz (fP -1.7dB) fIF = 45.75MHz fBeat = fIF 950kHz -50 -60 -60 -50 -40 -30 -20 -10 0 10 20 -30 -20 -10 0 10 20 RF level [dBm] RF level (SG Setting level) [dBm] - 19 - CXA3627ER Tuning Response Time VHF (Low) 95MHz VHF (High) 395MHz CP = 0 T = 47.2ms 5.0V/div Offset 10.0V -75.0000ms 25.0000ms 20.0ms/div 125.0000ms CP = 1 T = 15.0ms 5.0V/div Offset 10.0V -40.0000ms 10.0000ms 10.0ms/div 60.0000ms - 20 - CXA3627ER UHF 413MHz UHF 847MHz CP = 0 T = 63.6ms 5.0V/div Offset 10.0V -70.0000ms 30.0000ms 20.0ms/div 130.0000ms CP = 1 T = 20.2ms 5.0V/div Offset 10.0V -40.0000ms 10.0000ms 10.0ms/div 60.0000ms - 21 - CXA3627ER VHF (High) 395MHz VHF (Low) 95MHz CP = 0 T = 27.0ms 5.0V/div Offset 10.0V -110.0000ms -10.0000ms 20.0ms/div 90.0000ms CP = 1 T = 7.2ms 5.0V/div Offset 10.0V -45.0000ms 5.0000ms 10.0ms/div 55.0000ms - 22 - CXA3627ER UHF 847MHz UHF 413MHz CP = 0 T = 35.6ms 5.0V/div Offset 10.0V -110.0000ms -10.0000ms 20.0ms/div 90.0000ms CP = 1 T = 14.4ms 5.0V/div Offset 10.0V -90.0000ms 10.0000ms 20.0ms/div 110.0000ms - 23 - CXA3627ER IF output spectrum REF = -10.0dBm 10dB/div VHF (Low) fRF = 55MHz fLO = 100MHz RF input level: -40dBm CENTER 45.00100MHz RES BW 1.0kHz VBW 10Hz SPAN 50.00kHz SWP 30.0s REF = -10.0dBm 10dB/div VHF (High) fRF = 350MHz fLO = 395MHz RF input level: -40dBm CENTER 45.00350MHz RES BW 1.0kHz VBW 10Hz SPAN 50.00kHz SWP 30.0s REF = -0.0dBm 10dB/div UHF fRF = 800MHz fLO = 845MHz RF input level: -40dBm CENTER 45.00188MHz RES BW 1.0kHz VBW 10Hz SPAN 50.00kHz SWP 30.0s - 24 - CXA3627ER VHF Input Impedance j50 j25 j100 0 50 50MHz 7 8 1000p S11 350MHz -j25 -j100 -j50 UHF Input Impedance j50 j25 j100 0 50 10 350MHz 11 1000p S11 -j25 800MHz -j50 -j100 - 25 - CXA3627ER IF Output Impedance j50 j25 j100 0 45MHz 38MHz 50 -j25 -j100 -j50 - 26 - |
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